The present invention relates to a semiconductor device and a method of fabricating the semiconductor device. More particularly, the present invention relates to a layout arrangement and design for active regions and device isolation films of a semiconductor device, and to a method of fabricating the semiconductor device having the layout.
In recent years, there has been an increasing demand for large-capacity DRAMs (Dynamic Random Access Memories). However, a is size limit on the chip has placed a constraint on the increase of the DRAM capacity. When the chip size increases the number of chips per wafer should decrease, leading to the reduction in yield. Accordingly, great efforts have been made to change the cell layout so as to reduce the cell area and thus to integrate a larger number of memory cells in one wafer. With such efforts, the traditional 8F2 layout is now changing into the 6F2 layout.
FIG. 1 shows the 8F2 (or 8F2) layout for a semiconductor device according to the conventional art. Referring to FIG. 1, an active region 10 is formed of a rectangular or oval-shaped bar, and a device isolation film 20 defines active regions 10. In each of the active region 10, two word lines 30 and one bit line 40 intersect one another. Each active region 10 includes a bit-line contact region 13 and a storage node contact region 15. The bit-line contact region 13 defines a region where the active regions 10 and the bit line 40 are connected. The storage node contact region 15 defines a region where the active regions 10 and a capacitor (not shown) are connected.
A gate is formed at a portion of intersection of the word lines 30 and the active regions 10, and ions are implanted into the active regions 10 on either side of the gate to form a junction region for a source and a drain, with the source, the drain and the gate constituting a transistor. One transistor and one capacitor consist of one cell, and a relation between the minimum critical dimension (hereinafter referred to as ‘F’) of a semiconductor device and the cell area categorizes layouts of semiconductor devices as 8F2, 6F2 or 4F2.
In case of the semiconductor device shown in FIG. 1, the width of the active region 10 or word line 30 or bit line 40 becomes the minimum critical dimension F. Because a cell is 4F long in the transverse direction and 2F long in the longitudinal direction, the area of the cell becomes 4F×2F or 8F2. This cell layout is called 8F2.
Layouts for a DRAM device known so far include 8F2, 6F2 and 4F2, and among these the 4F2 layout has the highest cell density. In case of the 4F2 layout, however, the active regions should be formed in a cylindrical shape, a vertical type gate should be used, and a severe noise is generated between the lines. Thus, the 4F2 layout has many problems yet to be solved down the road before mass production.
Well-known examples of the 8F2 layout configuration include, for example, bar-shape, T-shape and star cell, and well-known examples of the 6F2 layout configuration include, for example, bar-shape and tilted bar-shape. There is an on-going effort to reduce the density of a unit cell in a DRAM device.